The reduction in scale of silicon technologies that has taken place in recent years has led to a large reduction in the supply voltages of transistors, and in the maximum voltage that is able to be applied across the terminals of the latter. The result of this is a severe restriction on the maximum admissible amplitude of the signals able to be generated or processed by circuits using these transistors. By way of example, 65 nm technology CMOS transistors are designed to withstand a drain-source voltage of 1.32 V. These transistors are generally supplied with 1.2 V; in the case of a cross-coupled differential pair oscillator, this would lead to a maximum drain-source voltage that reaches around 2.2 V at the positive peak of the oscillation. In order to ensure reliable operation, it is therefore necessary to limit the supply voltage to around 700 mV, and therefore the peak amplitude of the oscillation signal to just ±500 mV. For example, the article by J. L. González et al. ‘A 56-GHz LC-Tank VCO With 7% Tuning Range in 65-nm Bulk CMOS for Wireless HDMI’, RFIC 2009—IEEE Radio Frequency Integrated Circuits Symposium, 2009, describes a cross-coupled differential pair CMOS oscillator in which a PMOS transistor is used to supply a bias current at a voltage level lower than that supplying the circuit.
This results in a significant reduction in the signal-to-noise ratio (SNR), due in particular to the phase noise. This affects the spectral purity of the oscillation signal, which is undesirable in particular in telecommunications applications.
A first approach for addressing this problem is based on microelectronics technology. Those who developed this approach specifically introduced new families of transistors: dual-gate-oxide transistors (GO2) and lateral-drain-extended transistors (LDMOS) for CMOS technologies, and high-voltage bipolar transistors. In doing so, they were able to maintain voltages of the order of 1.5 V to 5 V, at the expense of an increase in manufacturing costs. By way of example, 28 nm UTBB FDSOI technology from STMicroelectronics has both single-oxide transistors (maximum voltage 1 V) and dual-oxide transistors (maximum voltage 1.5-1.8 V). However, these voltages (1.5-1.8 V) are still not sufficient to reach the SNR levels required in modern RF systems.
A second approach, as an alternative or in addition to the first, consists in designing assemblies that make it possible to distribute a supply voltage that is too high to be applied directly across the terminals of a single device between a plurality of transistors. For example, the article by J. Dang et al ‘A fully integrated 5.5 GHz cross-coupled VCO with high output power using 0.25 μm CMOS technology’ 2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS), Marseilles, 2014, pp. 255-258, describes an oscillator comprising a first differential pair of cross-coupled PMOS transistors and a second differential pair of cross-coupled NMOS transistors. The sources of the PMOS transistors of the first pair are connected to an electric power supply, and their drains are connected to those of the transistors of the second pair and to the terminals of a parallel LC resonant circuit. The sources of the transistors of the second pair are connected to ground. In this way, the supply voltage is shared between the two differential pairs, thereby making it possible to obtain an oscillatory signal with an amplitude higher than if only one pair were to be used. The drawback of this approach lies in the requirement to use PMOS transistors, the performance of which—in particular in terms of noise—is not as good as that of NMOS transistors.
Another possibility is that of using transistors in a ‘cascode’ configuration. However, this solution imposes frequency restrictions and impairs the efficiency of the circuit.